1. Field of the Invention
This invention relates to a system adapted to visually display image data and, more particularly, to a circuit and method adapted to automatically adjust the phase and frequency of a pixel clock derived from analog image data.
2. Description of the Related Art
Computers, televisions, video cameras, and other sources generate analog image data that is often digitized for eventual display on a digital display device. A pixel clock is necessary to properly digitize the analog image data. The pixel clock clocks the analog to digital converter that converts the analog image data into digital image data. Although the analog image data does not include the pixel clock, it does include a horizontal synchronization signal often used to generate the necessary pixel clock.
FIG. 1 is a block diagram of a circuit 100 including a phase locked loop (PLL) circuit 112 used to recover a pixel clock 128 from a reference or horizontal synchronization signal 110 for corresponding analog image data 132. The PLL circuit 112 includes a phase detector 114 serially connected to a loop filter 116 and a voltage controlled oscillator (VCO) 118. The PLL feedback loop comprises a programmable divider 120 that receives the VCO clock signal 122 and provides feedback signal 124 to the phase detector 114 responsive to a frequency adjust signal 136. The PLL circuit 112 is well known to those skilled in the art and will not be explained in further detail.
A phase adjust circuit 126 receives the VCO clock signal 122 and provides the pixel clock 128 to the analog to digital converter (ADC) 130 responsive to a phase adjust signal 138. The ADC 130 converts the analog image data 132 into digital image data 134 responsive to the pixel clock 128.
A digital data analysis circuit 140 generates the frequency and phase adjust signals 136 and 138, respectively, from an analysis of the digital data 134. To obtain a noise free image, the digital data 134 must be properly clocked. That is, the pixel clock 128 must have a phase and frequency appropriate for the analog data 132. The phase adjust circuit 126 uses the phase signal 138 to adjust the phase of the pixel clock 128 such that pixels sampled when the analog data 132 is stable and not in transition. The PLL circuit 112 uses the frequency signal 136 to adjust the frequency of the VCO clock 122 and consequently, the pixel clock 128. That is, such that the PLL circuit 112 is set to the proper multiple of the reference or horizontal synchronization signal 110.
The phase and frequency adjust circuit 100 relies on a feedback loop that examines the digital data 134 and makes adjustments to the phase and frequency of the pixel clock 128 until the digital data 134 is stable and noise free. One disadvantage associated with circuit 100 is that the phase and frequency adjustment might take several seconds to complete. Another disadvantage is that the error rate (or effectiveness) depends on the digital data 134. Yet another disadvantage is that the circuit 100 might not work correctly or consistently for images that do not completely fill the digital display device (not shown) at the expected resolution.
Accordingly, a need remains for an improved automatic phase and frequency adjust circuit and method.